1. Field of the Invention
This invention relates to a driving circuit for an active matrix display device, and more particularly to a scanning circuit for driving the pixel rows of a liquid crystal display device.
2. Description of the Prior Art
Generally, a conventional liquid crystal display (LCD) used for a display device of a television or a computer includes a matrix of liquid crystal cells that are arranged at the crossovers of data lines and select lines. The select lines are sequentially selected by a select line scanner to produce the horizontal lines of the display. The data lines apply the brightness (gray scale) signals to the columns of liquid crystal cells as the select lines are sequentially selected.
Preferably, the select line scanner, which selects the horizontal lines to be displayed, is fabricated directly onto the same substrate and at the same time as the liquid crystal cells. Also, since a large number of data select lines are required for a television or computer display, and the small pixel pitch limits the space available for laying out the driver circuitry, it is essential to keep the select line scanner as simple as possible.
FIG. 1 illustrates an example of a known select line scanner as described in U.S. Pat. No. 5,510,805, issued to Sywe N. Lee. This select line scanner includes 240 select line driver stages, r1 to r240, which are cascade-connected to each other and simultaneously connected to 240 row lines, ROW 1 to ROW 240, respectively.
Each select line driver stage r1 to r240 includes a transistor M6 for connecting a row line ROW i to a power supply VCC, and two transistors M7 and M8 for connecting a row line ROW i to a first ground VSS. The transistor M6 is turned off by two transistors M3 and MS after being turned on by a transistor M4. The transistor M7 is turned on when a transistor M1 is turned on and is turned off when a transistor M2 is turned on. Similarly, the two transistors M3 and M5 are turned on when the transistor M1 is turned on and are turned off when the transistor M2 is turned on. Further, the transistor M8 is turned on by two transistors M9 and M10 and is turned off by the transistor M1.
Next, each select line driver stage requires voltage signals on adjacent row lines ROW i-1 and ROW i+1, seven control/clock signals S.sub.1,0 to S.sub.3,0, S.sub.1,e to S.sub.3,e, and S.sub.4, two ground (i.e., negative(-)) voltage sources, VSS and VSS1, and a single supply (i.e., positive(+)) voltage source, VCC. The scanner also allows the voltage signal on the row lines ROW i to stably maintain a low logic state during an interval at which the first clock signal remains at a high logic state.
The conventional select line scanner disclosed in U.S. Pat. No. 5,510,805 has several disadvantages. One disadvantage is that the select line scanner requires numerous clock signals. Another disadvantage is that it requires many voltage signals on adjacent row lines and lengthens the rising time of the voltage signal on each row line. Further, since the select line scanner applies a high logic of voltage signal to two row lines simultaneously during a particular time interval, it may discharge a data signal charged into liquid crystal cells. Also, since each select line driver stage includes a relatively large number of transistors, the circuit configuration of the select line scanner is complicated.
A conventional shift register stage is shown in FIG. 2. The select line driver stage shown is described in U.S. Pat. No. 5,410,583, issued to Sherman Weisbrod, et al. While this shift register stage has a simpler configuration and fewer clock signals than the select line driver stage shown in FIG. 1, it still has its disadvantages.
This conventional shift register stage includes a pull-up transistor M6 for applying a high logic of voltage signal to row line ROW i, and a pull-down transistor M7 for applying a low logic of voltage signal to row line ROW i. The pull-up transistor M6 is turned on by a high level of the (i-1) row line signal g.sub.i-1 charged, via a transistor M1, into its gate, and allows a high level of a first clock signal C1 applied to its drain to be supplied to an (i) number row line. Then, the pull-up transistor M6 is turned off by a ground voltage VSS supplied via a transistor M5, to its gate when the (i+2) row line signal g.sub.i+2 is enabled into a high level state. At this time, the transistor M5 is turned on by the high level of the (i+2) row line signal g.sub.i+2 to discharge a voltage signal charged into the gate of the pull-up transistor M6 and into the ground VSS.
In this particular shift register stage, a supply voltage VDD is commonly applied, via a transistor M3, to the drain of transistor M4, the gates of transistor M2, and the pull-down transistor M7 during an interval at which the second clock signal C2 is enabled into a high level state. At this time, the pull-down transistor M7 is turned on by a supply voltage VDD applied, via transistor M3, to its gate, thereby discharging a voltage charged onto an (i) row line ROW i into ground VSS. Also, a transistor M2, whose gate is supplied with the supply voltage VDD by way of the transistor M3, is turned on, thereby discharging a voltage charged to the gate of the pull-up transistor M6 into ground VSS.
Meanwhile, transistor M4 is turned on when a high level of the (i-1) row line signal g.sub.i-1 is applied to its gate, thereby discharging a voltage charged to the gates of the pull-down transistor M7 and transistor M2 into the ground VSS. In the shift register stage as described above, the supply voltage VDD applied to the gate of the pull-down transistor M7 can be set to a threshold voltage V.sub.th sufficient to turn on the pull-down transistor M7.
The conventional shift register stage disclosed in U.S. Pat. No. 5,410,583 has disadvantages. In the shift register stage, since an enabled interval of the (i-1) row line signal g.sub.i-1 overlaps with that of the second clock signal C2, as shown in FIG. 3, four transistors M1, M2, M3, and M4 are turned on at the same time. Accordingly, to provide a sufficiently high voltage to the gate of the pull-up transistor M6, transistor M2 must have a small channel width and transistor M4 must have a large channel width.
Another disadvantage is that the channel width of the pull-up transistor M6 is limited by its gate voltage in addition to a load, (i.e. an impedance of a row line). If the transistor M3 has the same channel width as transistor M4, a voltage supplied to the gate of transistor M2 becomes VDD/2 and thereby reduces the power efficiency of the shift register stage. Finally, since transistors M3 and M4 are turned on at the same time an unnecessary waste of power occurs.